Nvidia Tegra 2/3/4

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SoCs

Nvidia Tegra 2
NVIDIA T20 chip
NVIDIA T20 chip
Manufacturer Nvidia
Name Tegra 2
Architecture armv7
CPU 2x 1.0/1.2 GHz ARM Cortex-A9
GPU Nvidia ULP Geforce
Year 2010
Process 40nm
Mainline yes
Community Page https://github.com/grate-driver
Components
CPU
Works
UART
Works
Storage
Works
USB
Works
Display
Works
GPU
Partial
Pinctrl
Works
I²C
Works
SPI
Works
Audio
Works
Video
Partial
Thermal
Works
Camera
Broken
Suspend
Works
Nvidia Tegra 3
NVIDIA T30 chip
NVIDIA T30 chip
Manufacturer Nvidia
Name Tegra 3
Architecture armv7
CPU 4x 1.2/1.4/1.6 GHz ARM Cortex-A9
GPU Nvidia ULP Geforce
Year 2011
Process 40nm
Mainline yes
Community Page https://github.com/grate-driver
Components
CPU
Works
UART
Works
Storage
Works
USB
Works
Display
Works
GPU
Partial
Pinctrl
Works
I²C
Works
SPI
Works
Audio
Works
Video
Partial
Thermal
Works
Camera
Broken
Suspend
Works
Nvidia Tegra 4
NVIDIA T114 chip
NVIDIA T114 chip
Manufacturer Nvidia
Name Tegra 4
Architecture armv7
CPU 4x 1.8-1.9 GHz Cortex-A15
GPU Nvidia ULP Geforce 72 cores
Year 2013
Process 28nm
Mainline yes
Community Page https://github.com/grate-driver
Components
CPU
Partial
UART
Works
Storage
Works
USB
Partial
Display
Works
GPU
Partial
Pinctrl
Works
I²C
Works
SPI
Partial
Audio
Works
Video
Partial
Thermal
Works
Camera
Broken
Suspend
Works


Generic device ports

These devices are combined into generic ports. Refer to chipset when looking for your device.

Device Codename Architecture Category Chipset
Nvidia Tegra ARMv7 nvidia-tegra-armv7 armv7 community Nvidia Tegra 2/3/4

Non-generic device ports

Other devices that are not combined into generic ports.

Tegra 2

Devices with a Tegra 2 Chipset

Device Mainline
Acer Iconia Tab A200 P
Acer Iconia Tab A500 Y
Lenovo ThinkPad Tablet
Samsung Captivate Glide P
Samsung Galaxy Tab 10.1 P

CPU

Tegra 2 uses two A9 cores without NEON instructions.

Tegra 3

Devices with a Nvidia Tegra 3 Chipset

Device Mainline
Acer Iconia Tab A700 P
Hisense Sero 7 Pro
HTC One X+
Medion Lifetab S9714
Microsoft Surface RT Y
Ouya, Inc. Ouya Y
Pegatron Chagall Y

Tegra 4

Devices with a Nvidia Tegra 4 Chipset

Device Mainline
Microsoft Surface 2 Y

GPU

Components (source)

  • Mesa-3D (minimal implementation, not complete enough (GL 1.4) to run XWayland (requires GL 2.1 or GLES2)
  • xf86-video-tegra (2D acceleration for X11, EXA)
  • libvdpau-tegra

Usability

Wayland:

  • Phosh works, but UI is accelerated trough llvmpipe (software rendering), thus is slow.
  • Plasma mobile not tested (please update)

X11:

  • Xfce4 and Mate desktop will run on 2D acceleration.
  • Hildon requires an OpenGL backend.
    • As of cogl 1.22.2 the clutter/cogl backend requires stencil buffers (EGL_STENCIL_SIZE). This not yet implemented in the grate-driver.

Video Decoding

Video Decoder Engine (VDE) was added to mainline kernel v4.16. The grate-driver includes hardware h264 decoding with libvdpau-tegra.

The vdpau driver does not support h264 videos encoded with:

  • weighted prediction
  • CABAC

Sample video that can be decoded with hardware acceleration: https://peach.blender.org/trailer-page/ 

$ mpv --hwdec=vdpau trailer_720p.mov
Using hardware decoding (vdpau).
VO: [vdpau] 1280x720 vdpau[yuv420p]

APX

Nvidia Tegra devices have APX mode which allows to flash/debrick a device even with broken bootloader. It also allows to sideload bootloader which is useful when porting a new bootloader.

Some devices have a key combination to enter this mode, some devices don't have one. We have a hook which alters two PMC registers which causes device to enter APX mode. It works on the most devices including some of those that don't have a key combination for APX.

Usage on Android devices: 

$ pmbootstrap initfs hook_add apx
$ pmbootstrap flasher boot

On Chrome OS devices and other not supporting fastboot boot command you will have to flash the image with kernel after enabling apx hook.

Participate development

Develop

Mesa3D Gallium driver

https://github.com/grate-driver/mesa

  • Host1x ABI rework (required before mesa implemenetation): (G. docs)
  • migrate from TGSI to NIR
  • establishing demos that work, where can be seen regression

New Device Trees

To generate the correct RAM timings for new Tegra 3 devices from known kernel sources, you can start from the known (downstream) RAM model code, and generate valid timings using this tool by Ion Agorria: https://gitlab.com/IonAgorria/tegra-timings-generator.

The #postmarketOS-on-transformers:matrix.org chat room will also be an excellent starting point for the porting of any new Tegra 2/3/4 device, also outside strictly the ASUS Transformer series

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