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See also '''[[Glossary]]'''. | |||
== A == | == A == | ||
* '''ACA''' - Accessory charger adapter | |||
'''ACA''' - Accessory charger adapter | * '''ACC''' - Application Clock Controller. Docs (e.g.) [https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt qcom,kpss-acc.txt] | ||
* '''ACM''' - Abstract control model (CDC subclass) | |||
'''ACM''' - Abstract control model (CDC subclass) | * '''ACU''' - Access control unit | ||
* '''ADC''' - Analog-to-digital converter | |||
'''ACU''' - Access control unit | * '''ADMA''' - Advanced direct memory access | ||
* '''ADP''' - Attach detection protocol | |||
'''ADC''' - Analog-to-digital converter | * '''ADSP''' - Audio Digital Signal Processor | ||
* '''AHB''' - Advanced high performance bus; AMBA high-speed bus | |||
'''ADMA''' - Advanced direct memory access | * '''AOSS''' - Always-On Subsystem | ||
* '''AP''' - Access port | |||
'''ADP''' - Attach detection protocol | * '''AP''' - Application processor | ||
* '''APC''' - Application processor core | |||
'''ADSP''' - Audio Digital Signal Processor | * '''APSS''' - Application processor subsystem | ||
* '''APU''' - Address protected unit | |||
'''AHB''' - Advanced high performance bus; AMBA high-speed bus | * '''APU''' - Advance protection unit | ||
* '''APU''' - Area Protection Unit | |||
'''AOSS''' - Always-On Subsystem | * '''ASM''' - Audio Stream Manager | ||
* '''ATB''' - Advanced trace bus | |||
'''AP''' - Access port | * '''ATB''' - AMBA trace Bus | ||
* '''aTCU''' - Application translation control unit | |||
'''AP''' - Application processor | * '''AVS''' - Adaptive voltage scaling | ||
* '''AXI''' - Advanced eXtensible Interface | |||
'''APC''' - Application processor core | * '''AUDIO_PD''' - Audio Process Protection Domain | ||
'''APSS''' - Application processor subsystem | |||
'''APU''' - Address protected unit | |||
'''APU''' - Advance protection unit | |||
'''APU''' - Area Protection Unit | |||
'''ATB''' - Advanced trace bus | |||
'''ATB''' - AMBA trace Bus | |||
'''aTCU''' - Application translation control unit | |||
'''AVS''' - Adaptive voltage scaling | |||
'''AXI''' - Advanced eXtensible Interface | |||
== B == | == B == | ||
* '''BAM''' - Bus access manager/module | |||
'''BAM''' - Bus access manager/module | * '''BASI''' - BAM-aware slave interface, between eDML and UART. Allows communication for data transfer coordination on the AHB bus. | ||
* '''BCR''' - Backward compatibility register. Each bit in this register enables a feature/fix, that changes the behavior of the UART controller in a manner that is not backward compatible. | |||
'''BASI''' - BAM-aware slave interface, between eDML and UART. Allows communication for data transfer coordination on the AHB bus. | * '''BIMC''' - Bus Integrated Memory Controller | ||
* '''BLLP''' - Banking or Low-Power Interval | |||
'''BCR''' - Backward compatibility register. Each bit in this register enables a feature/fix, that changes the behavior of the UART controller in a manner that is not backward compatible. | * '''BLSP''' - BAM low speed peripherals | ||
* '''BOB''' - BAM operational block | |||
'''BIMC''' - Bus Integrated Memory Controller | * '''BOM''' - Bus owner master | ||
* '''BP''' - Baseband processors | |||
'''BLLP''' - Banking or Low-Power Interval | * '''BR''' - Basic rate | ||
* '''BRIC''' - Reusable Bus and Interconnect Components | |||
'''BLSP''' - BAM low speed peripherals | * '''BTA''' - Bus Turnaround | ||
* '''BT''' - Bluetooth | |||
'''BOB''' - BAM operational block | * '''BU''' - Bus interface unit | ||
* '''BWC''' - Bandwidth Compression | |||
'''BOM''' - Bus owner master | |||
'''BP''' - Baseband processors | |||
'''BR''' - Basic rate | |||
'''BRIC''' - Reusable Bus and Interconnect Components | |||
'''BTA''' - Bus Turnaround | |||
'''BT''' - Bluetooth | |||
'''BU''' - Bus interface unit | |||
'''BWC''' - Bandwidth Compression | |||
== C == | == C == | ||
* '''CAHB''' - Control AHB bus | |||
'''CAHB''' - Control AHB bus | * '''CAMSS''' - Camera subsystem | ||
* '''CATS''' - Client-side address translation | |||
'''CAMSS''' - Camera subsystem | * '''CBC''' - Clock branch cell | ||
* '''CBC''' - Clock branch control | |||
'''CATS''' - Client-side address translation | * '''CBF''' - Coherent bus fabric | ||
* '''CCI''' - Camera control interface | |||
'''CBC''' - Clock branch cell | * '''CCI''' - (Core Cluster/Cache Coherent) Interconnect (NOT msm_bus/interconnect) | ||
* '''cCPU''' - Connectivity CPU | |||
'''CBC''' - Clock branch control | * '''CCR''' - Configuration control register | ||
* '''CDC''' - Codec, Coder/Decoder | |||
'''CCI''' - Camera control interface | * '''CDC''' - Communications device class (USB class) | ||
* '''CDP''' - Charging downstream port | |||
'''CCI''' - (Core Cluster/Cache Coherent) Interconnect (NOT msm_bus/interconnect) | * '''CGC''' - Clock gate control block | ||
* '''CID''' - CSID mapped ID, which is a combination of VC and DT | |||
'''cCPU''' - Connectivity CPU | * '''CPAS''' - Common platform architecture specification | ||
* '''CP''' - Correlation processor | |||
'''CCR''' - Configuration control register | * '''CPP''' - Camera post processing | ||
* '''CPR''' - Core power reduction | |||
'''CDC''' - Codec, Coder/Decoder | * '''CPSM''' - Command path state machine | ||
* '''CPU''' - Central processing unit | |||
'''CDC''' - Communications device class (USB class) | * '''CRC-32''' - 32-bit Cyclic Redundancy Check | ||
* '''CRC''' - Cyclic redundancy check | |||
'''CDP''' - Charging downstream port | * '''CRCI''' - Client rate control interface | ||
* '''CRIF''' - Core register interface | |||
'''CGC''' - Clock gate control block | * '''CRPC''' - Clock, reset, and power control | ||
* '''CSR''' - Control and status register(s) | |||
'''CID''' - CSID mapped ID, which is a combination of VC and DT | * '''CTI''' - cross-trigger interface | ||
* '''CTM''' - Cross Trigger Matrix | |||
'''CPAS''' - Common platform architecture specification | * '''CTS''' - Clear to send–incoming flow control signal | ||
* '''CURRX''' - Formerly known as valid_char_cnt. Amount of characters received in UART | |||
'''CP''' - Correlation processor | * '''CXO''' - Core crystal oscillator | ||
'''CPP''' - Camera post processing | |||
'''CPR''' - Core power reduction | |||
'''CPSM''' - Command path state machine | |||
'''CPU''' - Central processing unit | |||
'''CRC-32''' - 32-bit Cyclic Redundancy Check | |||
'''CRC''' - Cyclic redundancy check | |||
'''CRCI''' - Client rate control interface | |||
'''CRIF''' - Core register interface | |||
'''CRPC''' - Clock, reset, and power control | |||
'''CSR''' - Control and status register(s) | |||
'''CTI''' - cross-trigger interface | |||
'''CTM''' - Cross Trigger Matrix | |||
'''CTS''' - Clear to send–incoming flow control signal | |||
'''CURRX''' - Formerly known as valid_char_cnt. Amount of characters received in UART | |||
'''CXO''' - Core crystal oscillator | |||
== D == | == D == | ||
* '''DAC''' - digital-to-analog converter | |||
'''DAC''' - digital-to-analog converter | * '''DAHB''' - Data AHB bus | ||
* '''DAI''' - Digital Audio Interface | |||
'''DAHB''' - Data AHB bus | * '''DAP''' - Debug Access Port | ||
* '''DCD''' - Data contact detection | |||
'''DAP''' - Debug Access Port | * '''DCD''' - Dynamic clock divide | ||
* '''DCP''' - Dedicated charging port | |||
'''DCD''' - Data contact detection | * '''DCS''' - Display Command Set | ||
* '''DDR''' - Double data rate | |||
'''DCD''' - Dynamic clock divide | * '''DEHR''' - DMA Engine for Hardware Retention | ||
* '''DH''' - Diffie-Hellman key exchange | |||
'''DCP''' - Dedicated charging port | * '''DIS''' - Digital image stabilization | ||
* '''DLL''' - Delay-locked loop. Delay line. | |||
'''DCS''' - Display Command Set | * '''DMA''' - Direct memory access | ||
* '''DMB''' - Data memory barrier | |||
'''DDR''' - Double data rate | * '''DM''' - Data mover | ||
* '''DML''' - Data mover local | |||
'''DEHR''' - DMA Engine for Hardware Retention | * '''DMRX''' - A target value of an Rx transfer maximal length (in characters). Value is set | ||
* '''DMRX''' - event Occurs when CURRX value of an active RX transfer equals the DMRX | |||
'''DH''' - Diffie-Hellman key exchange | * '''DMRX''' - low event Occurs upon a write to the UART_DM_DMRX register with a value lower | ||
* '''DPCM''' - Differential pulse-code modulation compression | |||
'''DIS''' - Digital image stabilization | * '''DPE''' - DDR Protocol Engine | ||
* '''DPSM''' - Data path state machine | |||
'''DLL''' - Delay-locked loop. Delay line. | * '''dQH''' - Device queue head | ||
* '''DRAM''' - Dynamic random-access memory | |||
'''DMA''' - Direct memory access | * '''DRNG''' - Deterministic Random Number Generator | ||
* '''DRBG''' - Deterministic Random Bit Generator | |||
'''DMB''' - Data memory barrier | * '''DS''' - Default speed | ||
* '''DSI''' - Display Serial Interface | |||
'''DM''' - Data mover | * '''DSPS''' - Dedicated Sensors Processor Subsystem | ||
* '''DT''' - Data type | |||
'''DML''' - Data mover local | * '''dTD''' - Device transfer descriptor | ||
* '''DTE''' - DDR Test Engine | |||
'''DMRX''' - A target value of an Rx transfer maximal length (in characters). Value is set | |||
'''DMRX''' - event Occurs when CURRX value of an active RX transfer equals the DMRX | |||
'''DMRX''' - low event Occurs upon a write to the UART_DM_DMRX register with a value lower | |||
'''DPCM''' - Differential pulse-code modulation compression | |||
'''DPE''' - DDR Protocol Engine | |||
'''DPSM''' - Data path state machine | |||
'''dQH''' - Device queue head | |||
'''DRAM''' - Dynamic random-access memory | |||
'''DRNG''' - Deterministic Random Number Generator | |||
'''DRBG''' - Deterministic Random Bit Generator | |||
'''DS''' - Default speed | |||
'''DSI''' - Display Serial Interface | |||
'''DT''' - Data type | |||
'''dTD''' - Device transfer descriptor | |||
'''DTE''' - DDR Test Engine | |||
== E == | == E == | ||
* '''EBI''' - External bus interface | |||
'''EBI''' - External bus interface | * '''ECC''' - Error Correcting Code | ||
* '''ECT''' - Embedded cross-trigger | |||
'''ECC''' - Error Correcting Code | * '''ECNS''' - Echo cancellation and noise suppression | ||
* '''eDML''' - Bridge between BAM and QUP I 2 C/SPI interfaces. The eDML is a master on both sides and provides service to the multiple QUPs. | |||
'''ECT''' - Embedded cross-trigger | * '''EDR''' - Enhanced data rate | ||
* '''EE''' - Execution environment | |||
'''eDML''' - Bridge between BAM and QUP I 2 C/SPI interfaces. The eDML is a master on both sides and provides service to the multiple QUPs. | * '''eMMC''' - Embedded multimedia card | ||
* '''EOI''' - End of interrupt | |||
'''EDR''' - Enhanced data rate | * '''EOT''' - End of data transition | ||
* '''EoT''' - End of Transmission | |||
'''EE''' - Execution environment | * '''eSD''' - Embedded secure digital | ||
* '''eSDIO''' - Embedded secure digital input/output | |||
'''eMMC''' - Embedded multimedia card | * '''ETB''' - Embedded Trace Buffer | ||
* '''eTD''' - Enhanced transfer descriptor | |||
'''EOI''' - End of interrupt | * '''ETF''' - Embedded Trace FIFO | ||
* '''ЕТМ''' - Embedded trace macro | |||
'''EOT''' - End of data transition | * '''ETR''' - Embedded Trace Router | ||
'''EoT''' - End of Transmission | |||
'''eSD''' - Embedded secure digital | |||
'''eSDIO''' - Embedded secure digital input/output | |||
'''ETB''' - Embedded Trace Buffer | |||
'''eTD''' - Enhanced transfer descriptor | |||
'''ETF''' - Embedded Trace FIFO | |||
'''ЕТМ''' - Embedded trace macro | |||
'''ETR''' - Embedded Trace Router | |||
== F == | == F == | ||
* '''FDAHB''' - Fast data AHB bus | |||
'''FDAHB''' - Fast data AHB bus | * '''FEC''' - Forward error correction | ||
* '''FIQ''' - Fast interrupt request | |||
'''FEC''' - Forward error correction | * '''FM''' - Frequency modulation | ||
* '''FPB''' - Fast peripheral bus | |||
'''FIQ''' - Fast interrupt request | * '''FPS''' - Frames per second | ||
* '''FSM''' - Finite State Machine | |||
'''FM''' - Frequency modulation | * '''FSUSB''' - Full speed USB (USB 1.0/1.1 spec and above) | ||
'''FPB''' - Fast peripheral bus | |||
'''FPS''' - Frames per second | |||
'''FSM''' - Finite State Machine | |||
'''FSUSB''' - Full speed USB (USB 1.0/1.1 spec and above) | |||
== G == | == G == | ||
* '''GCC''' - Global clock controller | |||
'''GCC''' - Global clock controller | ** Kernel docs: [https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/qcom,gcc.txt qcom,gcc.txt] | ||
** DT Bindings: [https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/qcom,gcc.yaml qcom,gcc.yaml] | |||
* '''GDHS''' - Globally Distributed Head Switch | |||
* '''GDSC''' - Global distribution switch controller | |||
'''GDHS''' - Globally Distributed Head Switch | * <span id="GENI">'''GENI'''</span> - Generic Interface | ||
** Kernel docs: [https://www.kernel.org/doc/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt qcom,geni-se.txt] | |||
'''GDSC''' - Global distribution switch controller | * '''GFSK''' - Gaussian frequency-shift keying | ||
* <span id="GLINK">'''GLINK'''</span> | |||
<span id="GENI">'''GENI'''</span> - Generic Interface | ** Fifo based mechanism for communication between subsystems on Qualcomm platforms | ||
** Kernel docs: [https://www.kernel.org/doc/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt qcom,glink.txt] | |||
* '''GNSS''' - Global navigation subsystem | |||
'''GFSK''' - Gaussian frequency-shift keying | * '''GPIO''' - general-purpose input/output | ||
* '''GPO''' - general-purpose output | |||
<span id="GLINK">'''GLINK'''</span> | * '''GPU''' - Graphic Processing Unit | ||
* '''GSBI''' - General serial bus interface | |||
* '''gTCU''' - Graphics translation control unit | |||
'''GNSS''' - Global navigation subsystem | |||
'''GPIO''' - general-purpose input/output | |||
'''GPO''' - general-purpose output | |||
'''GPU''' - Graphic Processing Unit | |||
'''GSBI''' - General serial bus interface | |||
'''gTCU''' - Graphics translation control unit | |||
== H == | == H == | ||
* '''HBP''' - Horizontal back porch | |||
'''HBP''' - Horizontal back porch | * '''HFP''' - Horizontal front porch | ||
* '''HLOS''' - High-level operating system | |||
'''HFP''' - Horizontal front porch | * '''HPH''' - Headphone | ||
* '''HPI''' - High priority interrupt | |||
'''HLOS''' - High-level operating system | * '''HSA''' - Horizontal Sync Active | ||
* '''HS''' - High speed | |||
'''HPH''' - Headphone | * '''HS''' - High-speed USB (USB 2.0 spec and above) | ||
* '''HUM''' - Hit under miss | |||
'''HPI''' - High priority interrupt | * '''HW''' - Hardware | ||
'''HSA''' - Horizontal Sync Active | |||
'''HS''' - High speed | |||
'''HS''' - High-speed USB (USB 2.0 spec and above) | |||
'''HUM''' - Hit under miss | |||
'''HW''' - Hardware | |||
== I == | == I == | ||
* '''I2S''' - Inter-IC Sound, specification for serial, stereo audio transfer | |||
* '''IC''' - Integrated circuit | |||
* '''IDLT''' - Idle timer | |||
* '''IKE''' - Internet Key Exchange | |||
* '''IM''' - Integration module | |||
* '''IPA''' - Intermediate physical address | |||
* '''IPC''' - Interprocess communication | |||
* '''IPC''' - Interprocessor communication | |||
* '''IP''' - Intellectual Property (also known as a core or a block) | |||
* '''IrDA''' - Infrared data association | |||
* '''IRQ''' - Interrupt Request | |||
* '''ISDB''' - In silicon debugger | |||
* '''ISPIF''' - Image signal processors interface | |||
* '''ISR''' - Interrupt service routine | |||
* '''ITM''' - Interrupt transfer mode | |||
== J == | |||
* '''JDR''' - JTAG data registers | |||
''' | * '''JEITA''' - Japan Electronics and Information Technology Industries Association | ||
* '''JPEG''' - Joint Photographic Experts Group | |||
* '''JTAG''' - Joint Test Action Group (ANSI/ICEEE Std. 1149.1-1760) | |||
''' | |||
'''JPEG''' - Joint Photographic Experts Group | |||
'''JTAG''' - Joint Test Action Group (ANSI/ICEEE Std. 1149.1-1760) | |||
== K == | == K == | ||
* '''KVP''' - Key value pairs | |||
'''KVP''' - Key value pairs | |||
== L == | == L == | ||
* '''L2VIC''' - Second-level vector interrupt controller | |||
'''L2VIC''' - Second-level vector interrupt controller | * '''LA''' - Linux for Android | ||
* '''LAB/IBB''' - LCD Amoled Boost / Inverting Buck Boost (type of regulator) | |||
'''LA''' - Linux for Android | * '''LCD''' - Liquid Crystal Display | ||
* '''LDO''' - Low dropout (voltage regulator) | |||
'''LAB/IBB''' - LCD Amoled Boost / Inverting Buck Boost (type of regulator) | * '''LE''' - Low energy | ||
* '''LFSR''' - Liner Feedback Shift Register | |||
'''LCD''' - Liquid Crystal Display | * '''LPAE''' - Large physical address extension | ||
* '''LPA_IF''' - Low-Power Audio Interface | |||
'''LDO''' - Low dropout (voltage regulator) | * '''LPA''' - Low-Power Audio | ||
* '''LPASS''' - Low-Power Audio Sub-System | |||
'''LE''' - Low energy | * '''LP''' - Low-power | ||
* '''LPM''' - Link power management | |||
'''LFSR''' - Liner Feedback Shift Register | * '''LPM''' - Low-Power Memory | ||
* '''LS''' - USB Low speed USB (USB 1.0/1.1 spec and above) | |||
'''LPAE''' - Large physical address extension | * '''LTE''' - Long Term Evolution | ||
* '''LUT''' - Look up table | |||
'''LPA_IF''' - Low-Power Audio Interface | |||
'''LPA''' - Low-Power Audio | |||
'''LPASS''' - Low-Power Audio Sub-System | |||
'''LP''' - Low-power | |||
'''LPM''' - Link power management | |||
'''LPM''' - Low-Power Memory | |||
'''LS''' - USB Low speed USB (USB 1.0/1.1 spec and above) | |||
'''LTE''' - Long Term Evolution | |||
'''LUT''' - Look up table | |||
== M == | == M == | ||
* '''MAC''' - Media access control layer | |||
'''MAC''' - Media access control layer | * '''MBA''' - Modem boot authentication | ||
* '''MCLK''' - Secure digital interface clock | |||
'''MBA''' - Modem boot authentication | * '''MC''' - Micro controller | ||
* '''MCU''' - Minimum coded units | |||
'''MCLK''' - Secure digital interface clock | * '''MDP''' - Mobile Display Processor in MDSS | ||
* '''MDSS''' - Mobile Display Subsystem | |||
'''MC''' - Micro controller | * '''MGPI''' - Multi generic-event PMIC_ARB Interface | ||
* '''MI2S''' - Multichannel I2S | |||
'''MCU''' - Minimum coded units | * '''MIC''' - Microphone | ||
* '''MID''' - Master ID | |||
'''MDP''' - Mobile Display Processor in MDSS | * '''MIPI''' - Mobile Industry Processor Interface | ||
* '''MMC''' - Multimedia card | |||
'''MDSS''' - Mobile Display Subsystem | * '''MMCC''' - MultiMedia Clock Controller | ||
* '''MMSS''' - Multimedia subsystem | |||
'''MGPI''' - Multi generic-event PMIC_ARB Interface | * '''MND''' - M/N divider | ||
* '''MPM2''' - SoC Master power manager. Always-on power management block. | |||
'''MI2S''' - Multichannel I2S | * '''MPM''' - Master power management | ||
* '''MPM''' - Modem power manager | |||
'''MIC''' - Microphone | * '''MPP''' - Multipurpose pin | ||
* '''MPU''' - Memory Protection Unit | |||
'''MID''' - Master ID | * '''MPU''' - Microprocessing unit | ||
* '''MRC''' - Master reference code | |||
'''MIPI''' - Mobile Industry Processor Interface | * '''MSA''' - Modem self authentication | ||
* '''MSM''' - Mobile Station Modem | |||
'''MMC''' - Multimedia card | * '''MTP''' - Media transfer protocol (USB class) | ||
* '''MU-MIMO''' - Multi-user multiple-input, multiple-output; | |||
'''MMCC''' - MultiMedia Clock Controller | |||
'''MMSS''' - Multimedia subsystem | |||
'''MND''' - M/N divider | |||
'''MPM2''' - SoC Master power manager. Always-on power management block. | |||
'''MPM''' - Master power management | |||
'''MPM''' - Modem power manager | |||
'''MPP''' - Multipurpose pin | |||
'''MPU''' - Memory Protection Unit | |||
'''MPU''' - Microprocessing unit | |||
'''MRC''' - Master reference code | |||
'''MSA''' - Modem self authentication | |||
'''MSM''' - Mobile Station Modem | |||
'''MTP''' - Media transfer protocol (USB class) | |||
'''MU-MIMO''' - Multi-user multiple-input, multiple-output; | |||
== N == | == N == | ||
* '''NIDnT''' - Narrow Interface for Debug and Test | |||
'''NIDnT''' - Narrow Interface for Debug and Test | * '''NIST''' - National Institute of Standards and Technology | ||
* '''NIU''' - Network Interface Unit. The NIU is a NoC block that connects masters and | |||
'''NIST''' - National Institute of Standards and Technology | * '''NMEA''' - National marine electronics association | ||
* '''NoC''' - Network on Chip | |||
'''NIU''' - Network Interface Unit. The NIU is a NoC block that connects masters and | * '''NoC Master''' - Master Module or subsystem on the NoC capable of initiating transactions | ||
* '''NoC Slave''' - Module or subsystem on the NoC being accessed from masters. It is the | |||
'''NMEA''' - National marine electronics association | * '''NPA''' - Node power architecture | ||
* '''NS''' - Nonsecure | |||
'''NoC''' - Network on Chip | * '''NVIC''' - Nested vectored interrupt controller | ||
'''NoC Master''' - Master Module or subsystem on the NoC capable of initiating transactions | |||
'''NoC Slave''' - Module or subsystem on the NoC being accessed from masters. It is the | |||
'''NPA''' - Node power architecture | |||
'''NS''' - Nonsecure | |||
'''NVIC''' - Nested vectored interrupt controller | |||
== O == | == O == | ||
* '''OBEX''' - Object exchange (CDC subclass) | |||
'''OBEX''' - Object exchange (CDC subclass) | * '''OCIMEM''' - On Chip Internal Memory | ||
* '''OEM''' - Original equipment manufacturer | |||
'''OCIMEM''' - On Chip Internal Memory | * '''OOO''' - Out of order | ||
* '''OS''' - Operating system | |||
'''OEM''' - Original equipment manufacturer | * '''OTG''' - On-the-go | ||
* '''OVP''' - Over voltage protection | |||
'''OOO''' - Out of order | |||
'''OS''' - Operating system | |||
'''OTG''' - On-the-go | |||
'''OVP''' - Over voltage protection | |||
== P == | == P == | ||
* '''PA''' - Physical address | |||
'''PA''' - Physical address | * '''PBL''' - Primary boot loader | ||
* '''PCM''' - Pulse Code Modulation | |||
'''PBL''' - Primary boot loader | * '''PCNOC''' - Peripheral and system Configuration NoC | ||
* '''PDM''' - Pulse Density Modulation | |||
'''PCM''' - Pulse Code Modulation | * '''PDN''' - Power distribution network | ||
* '''PD''' - Power domain | |||
'''PCNOC''' - Peripheral and system Configuration NoC | * '''PHSS''' - Peripheral subsystem | ||
* '''PHY''' - Physical Layer | |||
'''PDM''' - Pulse Density Modulation | * '''PIL''' - Peripheral image loader | ||
* '''PK''' - Public key | |||
'''PDN''' - Power distribution network | * '''PLL''' - Phase Locked Loop | ||
* '''PMIC_ARB''' - PMIC arbiter | |||
'''PD''' - Power domain | * '''PMIC''' - Power-Management IC. May include analog audio components such as ADC, | ||
* '''POR''' - Power-on reset | |||
'''PHSS''' - Peripheral subsystem | * '''PPI''' - Private peripheral interrupt | ||
* '''PRNG''' - Pseudo Random Number Generator | |||
'''PHY''' - Physical Layer | * '''PSCBC''' - Power switch clock branch cell | ||
* '''PTW''' - Page table walk | |||
'''PIL''' - Peripheral image loader | * '''PubCSR''' - Public configuration and status register | ||
* '''PVC''' - PMIC voltage control | |||
'''PK''' - Public key | * '''PD-MAPPER''' - Protection Domain Mapper | ||
'''PLL''' - Phase Locked Loop | |||
'''PMIC_ARB''' - PMIC arbiter | |||
'''PMIC''' - Power-Management IC. May include analog audio components such as ADC, | |||
'''POR''' - Power-on reset | |||
'''PPI''' - Private peripheral interrupt | |||
'''PRNG''' - Pseudo Random Number Generator | |||
'''PSCBC''' - Power switch clock branch cell | |||
'''PTW''' - Page table walk | |||
'''PubCSR''' - Public configuration and status register | |||
'''PVC''' - PMIC voltage control | |||
== Q == | == Q == | ||
* '''QCOM''' - Qualcomm | |||
'''QCOM''' - Qualcomm | * '''QDSP6''' - Qualcomm digital signal processor | ||
* '''QDSS''' - Qualcomm Debug Subsystem | |||
'''QDSP6''' - Qualcomm digital signal processor | * '''QFPROM''' - Qualcomm fuse-programmable read-only memory | ||
* '''QFROM''' - Qualcomm fuse programmable read-only memory | |||
'''QDSS''' - Qualcomm Debug Subsystem | * '''QGIC2''' - Qualcomm generic interrupt controller; compliant to ARM GIC v2.0 spec | ||
* '''QGIC''' - Qualcomm Generic Interrupt Controller | |||
'''QFPROM''' - Qualcomm fuse-programmable read-only memory | * '''QMP''' - Qualcomm Mailbox Protocol | ||
* '''QoS''' - Quality of service | |||
'''QFROM''' - Qualcomm fuse programmable read-only memory | * '''QSB''' - Qualcomm SoC Bus | ||
* '''QTimer''' - Qualcomm timer | |||
'''QGIC2''' - Qualcomm generic interrupt controller; compliant to ARM GIC v2.0 spec | * '''QTI''' - Qualcomm Technologies, Inc. | ||
* '''QuIC''' - Qualcomm Innovation Center | |||
'''QGIC''' - Qualcomm Generic Interrupt Controller | * '''QUP''' - Qualcomm Universal Peripheral | ||
** Kernel docs: [https://www.kernel.org/doc/Documentation/devicetree/bindings/spi/qcom%2Cspi-qup.txt qcom,spi-qup.txt], [https://www.kernel.org/doc/Documentation/devicetree/bindings/i2c/qcom%2Ci2c-qup.txt qcom,i2c-qup.txt], | |||
'''QMP''' - Qualcomm Mailbox Protocol | ** See also: [[# GENI]] | ||
'''QoS''' - Quality of service | |||
'''QSB''' - Qualcomm SoC Bus | |||
'''QTimer''' - Qualcomm timer | |||
'''QTI''' - Qualcomm Technologies, Inc. | |||
'''QUP''' - Qualcomm Universal Peripheral | |||
== R == | == R == | ||
* '''RAM''' - Random Access Memory | |||
'''RAM''' - Random Access Memory | * '''RAZ''' - Read As Zero | ||
* '''RBCPR''' - Rapid bridge core power reduction | |||
'''RAZ''' - Read As Zero | * '''RCG''' - Root clock generator | ||
* '''RCS''' - Response capable slaves | |||
'''RBCPR''' - Rapid bridge core power reduction | * '''RDI''' - data Raw dump interface embedded data passed to the image pipe along the pixel | ||
* '''RDS''' - Radio data system | |||
'''RCG''' - Root clock generator | * '''RFE''' - Reference frame engine | ||
* '''RFR''' - ReadyForReceive, outgoing flow control signal | |||
'''RCS''' - Response capable slaves | * '''RID''' - ID resistor | ||
* '''RIF''' - Register Interface | |||
'''RDI''' - data Raw dump interface embedded data passed to the image pipe along the pixel | * '''RNG''' - Random Number Generator | ||
* <span id="RPM">'''RPM'''</span> - Resource and Power Manager | |||
'''RDS''' - Radio data system | ** remoteproc (cortex M3 on msm8916) | ||
** The sw running on it allows each component in the system to vote for resources such as clocks, regulators, and bus frequencies | |||
'''RFE''' - Reference frame engine | ** Not to be confused with RPMSG | ||
** Controlled with the <code>"rpm_requests"</code> SMD channel, either over [[#GLINK]] or [[#SMD]] | |||
'''RFR''' - ReadyForReceive, outgoing flow control signal | ** Kernel docs: [https://www.kernel.org/doc/Documentation/devicetree/bindings/mfd/qcom-rpm.txt qcom-rpm.txt] | ||
* '''RPMCC''' - [[#RPM]] Clock Controller | |||
'''RID''' - ID resistor | * '''RPMH''' - RPM Hardened (used in newer SoCs, like sdm845) | ||
* '''RPMPD''' - RPM Power Domains | |||
'''RIF''' - Register Interface | * '''RPU''' - Register protection unit | ||
* '''RST_CTL''' - Reset controller | |||
'''RNG''' - Random Number Generator | * '''RXLEV''' - This is the name of the watermark interrupt, asserted when amount of data words in the Rx FIFO exceeds the value in UART_DM_RFWR register. It is also referred to as the value in UART_DM_RFWR register. | ||
<span id="RPM">'''RPM'''</span> - Resource and Power Manager | |||
'''RPMCC''' - [[#RPM]] Clock Controller | |||
'''RPMH''' - RPM Hardened (used in newer SoCs, like sdm845) | |||
'''RPMPD''' - RPM Power Domains | |||
'''RPU''' - Register protection unit | |||
'''RST_CTL''' - Reset controller | |||
'''RXLEV''' - This is the name of the watermark interrupt, asserted when amount of data words in the Rx FIFO exceeds the value in UART_DM_RFWR register. It is also referred to as the value in UART_DM_RFWR register. | |||
== S == | == S == | ||
* '''SAW2''' - SPM AVS wrapper. Docs: [https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt qcom,saw2.txt] | |||
* '''SAW''' - SPM and AVS (Subystem Power Manager and Adaptive Voltage Scaling) | |||
* '''SBL''' - Secondary boot loader | |||
'''SAW2''' - SPM AVS wrapper | * '''SCMO''' - SDRAM Control and Memory Organizer | ||
* '''SC''' - Single character–packing/unpacking of one character per word | |||
'''SAW''' - SPM and AVS | * '''SC''' - Snapdragon Compute(r?) | ||
* '''SDCC''' - Secure digital card controller | |||
* '''SDCDC''' - Programmable delay line | |||
* '''SDC''' - Secure digital card | |||
'''SBL''' - Secondary boot loader | * '''SDHCI''' - Secure digital host controller interface | ||
* '''SDIO''' - Secure digital input/output | |||
'''SCMO''' - SDRAM Control and Memory Organizer | * '''SDP''' - Standard downstream port | ||
* '''SDE''' - Snapdragon Display Engine | |||
'''SC''' - Single character–packing/unpacking of one character per word | * '''SDR''' - Single data rate | ||
* '''SD''' - Secure digital | |||
'''SC''' - Snapdragon Compute(r?) | * '''SDM''' - Snapdragon Mobile | ||
* '''SEV''' - Send event | |||
'''SDCC''' - Secure digital card controller | * '''SGI''' - Software generated interrupt | ||
* '''SHA''' - Secure Hash Algorithm | |||
'''SDCDC''' - Programmable delay line | * '''SHKE''' - SDRAM Housekeeping Engine | ||
* '''SIF''' - Standard Input Format | |||
'''SDC''' - Secure digital card | * '''SIMD''' - Single instruction multiple data | ||
* '''SIM''' - Subscriber identity module | |||
'''SDHCI''' - Secure digital host controller interface | * '''Single''' - character mode A UART packing/unpacking mode for both Rx and Tx channels | ||
* '''SLPC''' - Sleep controller | |||
'''SDIO''' - Secure digital input/output | * '''SLPI''' - Sensor Low Power Island | ||
* <span id="SMD">'''SMD'''</span> - Shared memory driver | |||
'''SDP''' - Standard downstream port | * '''SMEM''' - Shared memory | ||
* '''SMMU''' - System memory management unit | |||
'''SDR''' - Single data rate | * '''SM''' - Sample memory | ||
* '''SNOC''' - System NoC | |||
'''SD''' - Secure digital | * '''SOC''' - System on Chip | ||
* '''SOT''' - Start of data transition | |||
'''SDM''' - Snapdragon Mobile | * '''SPB''' - Simple peripheral bus specification by Microsoft | ||
* '''SPI''' - Shared peripheral interrupt | |||
'''SEV''' - Send event | * '''SPKR''' - Speaker (loudspeaker) | ||
* '''SPMI''' - System power management interface | |||
'''SGI''' - Software generated interrupt | * '''SPM''' - Subsystem Power Manager | ||
* '''SPS''' - Smart peripheral subsystem | |||
'''SHA''' - Secure Hash Algorithm | * '''SROT''' - Secured root of trust | ||
* '''SSBI''' - Single-wire serial bus interface | |||
'''SHKE''' - SDRAM Housekeeping Engine | * '''SSC''' - Snapdragon Sensor Core | ||
* '''SSL''' - Secure Sockets Layer | |||
'''SIF''' - Standard Input Format | * '''SSPP''' - Source surface processing pipe | ||
* '''SS''' - Subsystem | |||
'''SIMD''' - Single instruction multiple data | * '''STB''' - Sensor timing strobe | ||
* '''STM''' - System Trace Macrocell | |||
'''SIM''' - Subscriber identity module | * '''Sub-block''' - Any section of RTL code; it is typically a unit not sufficiently large and independent | ||
* '''SVS''' - Static voltage scaling | |||
'''Single''' - character mode A UART packing/unpacking mode for both Rx and Tx channels | * '''SWD''' - Serial Wire Debug | ||
* '''SWFI''' - Suspend and wait for interrupt | |||
'''SLPC''' - Sleep controller | * '''SW''' - Software | ||
* '''SENSORS_PD''' - Sensors Process Protection Domain | |||
'''SLPI''' - Sensor Low Power Island | |||
<span id="SMD">'''SMD'''</span> - Shared memory driver | |||
'''SMEM''' - Shared memory | |||
'''SMMU''' - System memory management unit | |||
'''SM''' - Sample memory | |||
'''SNOC''' - System NoC | |||
'''SOC''' - System on Chip | |||
'''SOT''' - Start of data transition | |||
'''SPB''' - Simple peripheral bus specification by Microsoft | |||
'''SPI''' - Shared peripheral interrupt | |||
'''SPKR''' - Speaker (loudspeaker) | |||
'''SPMI''' - System power management interface | |||
'''SPM''' - Subsystem | |||
'''SPS''' - Smart peripheral subsystem | |||
'''SROT''' - Secured root of trust | |||
'''SSBI''' - Single-wire serial bus interface | |||
'''SSL''' - Secure Sockets Layer | |||
'''SSPP''' - Source surface processing pipe | |||
'''SS''' - Subsystem | |||
'''STB''' - Sensor timing strobe | |||
'''STM''' - System Trace Macrocell | |||
'''Sub-block''' - Any section of RTL code; it is typically a unit not sufficiently large and independent | |||
'''SVS''' - Static voltage scaling | |||
'''SWD''' - Serial Wire Debug | |||
'''SWFI''' - Suspend and wait for interrupt | |||
'''SW''' - Software | |||
== T == | == T == | ||
* '''TAS''' - Telephony Application Server (VoLTE) | |||
'''TBU''' - Translation buffer unit; local page table caches | * '''TBU''' - Translation buffer unit; local page table caches | ||
* '''TCM''' - Tightly coupled memory | |||
'''TCM''' - Tightly coupled memory | * '''TCSR''' - Top level Control and Status Register | ||
** Provides access for configuration and mux settings for a variety of peripherals. | |||
'''TCSR''' - Top level Control and Status Register | ** Kernel docs: [https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/mfd/qcom%2Ctcsr.yaml qcom,tcsr.yaml] | ||
* '''TCU''' - Translation control unit; central page table caches | |||
* '''TCXO''' - Crystal oscillator | |||
* '''TDM''' - Time-division Multiplexing | |||
'''TCU''' - Translation control unit; central page table caches | * '''TE''' - Tearing Effect | ||
* '''TLB''' - Translation lookaside buffer | |||
'''TCXO''' - Crystal oscillator | * <span id="TLMM">'''TLMM'''</span>- Top-Level Mode Multiplexer | ||
** provides pin multiplexing and pin controller | |||
'''TDM''' - Time-division Multiplexing | ** can change signal routing on almost any physical pin | ||
* '''TLS''' - Transport Layer Security | |||
'''TE''' - Tearing Effect | * '''TPIU''' - Trace Port Interface Unit | ||
* '''TRM''' - Technical reference manual | |||
'''TLB''' - Translation lookaside buffer | * '''TSENS''' - Temperature sensor | ||
* '''TSIF''' - Transport stream interface | |||
* '''TXLEV''' - This is the name of the watermark interrupt, asserted when amount of | |||
* '''TZ''' - TrustZone | |||
'''TLS''' - Transport Layer Security | |||
'''TPIU''' - Trace Port Interface Unit | |||
'''TRM''' - Technical reference manual | |||
'''TSENS''' - Temperature sensor | |||
'''TSIF''' - Transport stream interface | |||
'''TXLEV''' - This is the name of the watermark interrupt, asserted when amount of | |||
'''TZ''' - TrustZone | |||
== U == | == U == | ||
* '''UART_DM''' - Universal asynchronous receiver transmitter with data mover interface | |||
'''UART_DM''' - Universal asynchronous receiver transmitter with data mover interface | * '''UART''' - Universal asynchronous receiver/transmitter | ||
* '''UAR''' - Universal asynchronous reset | |||
'''UART''' - Universal asynchronous receiver/transmitter | * '''UHS''' - Ultra high speed | ||
* '''UIM''' - User identity module | |||
'''UAR''' - Universal asynchronous reset | * '''ULPI''' - UTMI+ low pin interface | ||
* '''ULPM''' - Ultra-low power mode, generally known as standby | |||
'''UHS''' - Ultra high speed | * '''ULT''' - Audio Ultra Low-Power Audio, a version of LPASS | ||
* '''USB''' - Universal serial bus | |||
'''UIM''' - User identity module | * '''UTMI''' - USB 2.0 transceiver macrocell interface | ||
* '''USER_PD''' - Dynamic User Protection Domain, cases like SNPE or CV | |||
'''ULPI''' - UTMI+ low pin interface | * '''UE''' - User Equipment (VoLTE) | ||
* '''UT''' - UE to TAS (VoLTE) | |||
'''ULPM''' - Ultra-low power mode, generally known as standby | |||
'''ULT''' - Audio Ultra Low-Power Audio, a version of LPASS | |||
'''USB''' - Universal serial bus | |||
'''UTMI''' - USB 2.0 transceiver macrocell interface | |||
== V == | == V == | ||
* '''VA''' - Virtual address | |||
'''VA''' - Virtual address | * '''VBIF''' - Virtualizing Bus Interface | ||
* '''VBUS''' - USB bus voltage (5 V for USB 2.0) | |||
'''VBIF''' - Virtualizing Bus Interface | * '''VCO''' - Voltage-controlled oscillator | ||
* '''VC''' - Virtual channel | |||
'''VBUS''' - USB bus voltage (5 V for USB 2.0) | * '''VDD_CX''' - Digital power domain directly supplied by CXO | ||
* '''VDD_MX''' - Memory power domain | |||
'''VCO''' - Voltage-controlled oscillator | * '''VDD''' - Supply voltage | ||
* '''VENCDEC''' - Video encoder/decoder | |||
'''VC''' - Virtual channel | * '''VFE''' - Video Front End | ||
* '''VFR''' - Vocoder Frame Reference | |||
'''VDD_CX''' - Digital power domain directly supplied by CXO | * '''VLIW''' - Very long instruction word | ||
* '''VLS''' - Voltage level shifter | |||
'''VDD_MX''' - Memory power domain | * '''VMIDMT''' - Virtual machine ID mapping table | ||
* '''VMID''' - Virtual machine identification | |||
'''VDD''' - Supply voltage | * '''VPP''' - Video pixel processor | ||
* '''VSP''' - Video stream processor | |||
'''VENCDEC''' - Video encoder/decoder | * '''VS''' - Video Share (VoLTE) | ||
* '''VT''' - Video Telephony (VoLTE) | |||
'''VFE''' - Video Front End | |||
'''VFR''' - Vocoder Frame Reference | |||
'''VLIW''' - Very long instruction word | |||
'''VLS''' - Voltage level shifter | |||
'''VMIDMT''' - Virtual machine ID mapping table | |||
'''VMID''' - Virtual machine identification | |||
'''VPP''' - Video pixel processor | |||
'''VSP''' - Video stream processor | |||
== W == | == W == | ||
* '''WAPI''' - WLAN Authentication and Privacy Infrastructure | |||
'''WAPI''' - WLAN Authentication and Privacy Infrastructure | * '''WB''' - Write buffering | ||
* '''WCSSS''' - Wireless connectivity sub system software | |||
'''WB''' - Write buffering | * '''WCNSS'''/'''WCSS''' - Wireless Connectivity Subsystem | ||
* '''WDOG''' - Watchdog | |||
'''WCSSS''' - Wireless connectivity sub system software | * '''WDT''' - Watchdog Timer | ||
* '''WFE''' - Wait for event | |||
'''WCSS''' - Wireless Connectivity Subsystem | * '''WFI''' - Wait for interrupt | ||
* '''WI''' - Write Ignored | |||
'''WDOG''' - Watchdog | * '''WM''' - Write Master | ||
* '''WLAN''' - Wireless local area network | |||
'''WDT''' - Watchdog Timer | |||
'''WFE''' - Wait for event | |||
'''WFI''' - Wait for interrupt | |||
'''WI''' - Write Ignored | |||
'''WLAN''' - Wireless local area network | |||
== X == | == X == | ||
* '''XO''' - Crystal (19.2 MHz) | |||
'''XO''' - Crystal (19.2 MHz) | * '''xPU''' - Protection Unit (x = multiple varieties; address, memory, register) | ||
** basic overview : https://www.qualcomm.com/media/documents/files/an-introduction-to-access-control-on-qualcomm-snapdragon-platforms.pdf | |||
'''xPU''' - Protection Unit (x = multiple varieties; address, memory, register) | |||
== Y == | == Y == | ||
== Z == | == Z == | ||
[[Category:Technical Reference]] |
Latest revision as of 16:29, 13 February 2025
See also Glossary.
A
- ACA - Accessory charger adapter
- ACC - Application Clock Controller. Docs (e.g.) qcom,kpss-acc.txt
- ACM - Abstract control model (CDC subclass)
- ACU - Access control unit
- ADC - Analog-to-digital converter
- ADMA - Advanced direct memory access
- ADP - Attach detection protocol
- ADSP - Audio Digital Signal Processor
- AHB - Advanced high performance bus; AMBA high-speed bus
- AOSS - Always-On Subsystem
- AP - Access port
- AP - Application processor
- APC - Application processor core
- APSS - Application processor subsystem
- APU - Address protected unit
- APU - Advance protection unit
- APU - Area Protection Unit
- ASM - Audio Stream Manager
- ATB - Advanced trace bus
- ATB - AMBA trace Bus
- aTCU - Application translation control unit
- AVS - Adaptive voltage scaling
- AXI - Advanced eXtensible Interface
- AUDIO_PD - Audio Process Protection Domain
B
- BAM - Bus access manager/module
- BASI - BAM-aware slave interface, between eDML and UART. Allows communication for data transfer coordination on the AHB bus.
- BCR - Backward compatibility register. Each bit in this register enables a feature/fix, that changes the behavior of the UART controller in a manner that is not backward compatible.
- BIMC - Bus Integrated Memory Controller
- BLLP - Banking or Low-Power Interval
- BLSP - BAM low speed peripherals
- BOB - BAM operational block
- BOM - Bus owner master
- BP - Baseband processors
- BR - Basic rate
- BRIC - Reusable Bus and Interconnect Components
- BTA - Bus Turnaround
- BT - Bluetooth
- BU - Bus interface unit
- BWC - Bandwidth Compression
C
- CAHB - Control AHB bus
- CAMSS - Camera subsystem
- CATS - Client-side address translation
- CBC - Clock branch cell
- CBC - Clock branch control
- CBF - Coherent bus fabric
- CCI - Camera control interface
- CCI - (Core Cluster/Cache Coherent) Interconnect (NOT msm_bus/interconnect)
- cCPU - Connectivity CPU
- CCR - Configuration control register
- CDC - Codec, Coder/Decoder
- CDC - Communications device class (USB class)
- CDP - Charging downstream port
- CGC - Clock gate control block
- CID - CSID mapped ID, which is a combination of VC and DT
- CPAS - Common platform architecture specification
- CP - Correlation processor
- CPP - Camera post processing
- CPR - Core power reduction
- CPSM - Command path state machine
- CPU - Central processing unit
- CRC-32 - 32-bit Cyclic Redundancy Check
- CRC - Cyclic redundancy check
- CRCI - Client rate control interface
- CRIF - Core register interface
- CRPC - Clock, reset, and power control
- CSR - Control and status register(s)
- CTI - cross-trigger interface
- CTM - Cross Trigger Matrix
- CTS - Clear to send–incoming flow control signal
- CURRX - Formerly known as valid_char_cnt. Amount of characters received in UART
- CXO - Core crystal oscillator
D
- DAC - digital-to-analog converter
- DAHB - Data AHB bus
- DAI - Digital Audio Interface
- DAP - Debug Access Port
- DCD - Data contact detection
- DCD - Dynamic clock divide
- DCP - Dedicated charging port
- DCS - Display Command Set
- DDR - Double data rate
- DEHR - DMA Engine for Hardware Retention
- DH - Diffie-Hellman key exchange
- DIS - Digital image stabilization
- DLL - Delay-locked loop. Delay line.
- DMA - Direct memory access
- DMB - Data memory barrier
- DM - Data mover
- DML - Data mover local
- DMRX - A target value of an Rx transfer maximal length (in characters). Value is set
- DMRX - event Occurs when CURRX value of an active RX transfer equals the DMRX
- DMRX - low event Occurs upon a write to the UART_DM_DMRX register with a value lower
- DPCM - Differential pulse-code modulation compression
- DPE - DDR Protocol Engine
- DPSM - Data path state machine
- dQH - Device queue head
- DRAM - Dynamic random-access memory
- DRNG - Deterministic Random Number Generator
- DRBG - Deterministic Random Bit Generator
- DS - Default speed
- DSI - Display Serial Interface
- DSPS - Dedicated Sensors Processor Subsystem
- DT - Data type
- dTD - Device transfer descriptor
- DTE - DDR Test Engine
E
- EBI - External bus interface
- ECC - Error Correcting Code
- ECT - Embedded cross-trigger
- ECNS - Echo cancellation and noise suppression
- eDML - Bridge between BAM and QUP I 2 C/SPI interfaces. The eDML is a master on both sides and provides service to the multiple QUPs.
- EDR - Enhanced data rate
- EE - Execution environment
- eMMC - Embedded multimedia card
- EOI - End of interrupt
- EOT - End of data transition
- EoT - End of Transmission
- eSD - Embedded secure digital
- eSDIO - Embedded secure digital input/output
- ETB - Embedded Trace Buffer
- eTD - Enhanced transfer descriptor
- ETF - Embedded Trace FIFO
- ЕТМ - Embedded trace macro
- ETR - Embedded Trace Router
F
- FDAHB - Fast data AHB bus
- FEC - Forward error correction
- FIQ - Fast interrupt request
- FM - Frequency modulation
- FPB - Fast peripheral bus
- FPS - Frames per second
- FSM - Finite State Machine
- FSUSB - Full speed USB (USB 1.0/1.1 spec and above)
G
- GCC - Global clock controller
- Kernel docs: qcom,gcc.txt
- DT Bindings: qcom,gcc.yaml
- GDHS - Globally Distributed Head Switch
- GDSC - Global distribution switch controller
- GENI - Generic Interface
- Kernel docs: qcom,geni-se.txt
- GFSK - Gaussian frequency-shift keying
- GLINK
- Fifo based mechanism for communication between subsystems on Qualcomm platforms
- Kernel docs: qcom,glink.txt
- GNSS - Global navigation subsystem
- GPIO - general-purpose input/output
- GPO - general-purpose output
- GPU - Graphic Processing Unit
- GSBI - General serial bus interface
- gTCU - Graphics translation control unit
H
- HBP - Horizontal back porch
- HFP - Horizontal front porch
- HLOS - High-level operating system
- HPH - Headphone
- HPI - High priority interrupt
- HSA - Horizontal Sync Active
- HS - High speed
- HS - High-speed USB (USB 2.0 spec and above)
- HUM - Hit under miss
- HW - Hardware
I
- I2S - Inter-IC Sound, specification for serial, stereo audio transfer
- IC - Integrated circuit
- IDLT - Idle timer
- IKE - Internet Key Exchange
- IM - Integration module
- IPA - Intermediate physical address
- IPC - Interprocess communication
- IPC - Interprocessor communication
- IP - Intellectual Property (also known as a core or a block)
- IrDA - Infrared data association
- IRQ - Interrupt Request
- ISDB - In silicon debugger
- ISPIF - Image signal processors interface
- ISR - Interrupt service routine
- ITM - Interrupt transfer mode
J
- JDR - JTAG data registers
- JEITA - Japan Electronics and Information Technology Industries Association
- JPEG - Joint Photographic Experts Group
- JTAG - Joint Test Action Group (ANSI/ICEEE Std. 1149.1-1760)
K
- KVP - Key value pairs
L
- L2VIC - Second-level vector interrupt controller
- LA - Linux for Android
- LAB/IBB - LCD Amoled Boost / Inverting Buck Boost (type of regulator)
- LCD - Liquid Crystal Display
- LDO - Low dropout (voltage regulator)
- LE - Low energy
- LFSR - Liner Feedback Shift Register
- LPAE - Large physical address extension
- LPA_IF - Low-Power Audio Interface
- LPA - Low-Power Audio
- LPASS - Low-Power Audio Sub-System
- LP - Low-power
- LPM - Link power management
- LPM - Low-Power Memory
- LS - USB Low speed USB (USB 1.0/1.1 spec and above)
- LTE - Long Term Evolution
- LUT - Look up table
M
- MAC - Media access control layer
- MBA - Modem boot authentication
- MCLK - Secure digital interface clock
- MC - Micro controller
- MCU - Minimum coded units
- MDP - Mobile Display Processor in MDSS
- MDSS - Mobile Display Subsystem
- MGPI - Multi generic-event PMIC_ARB Interface
- MI2S - Multichannel I2S
- MIC - Microphone
- MID - Master ID
- MIPI - Mobile Industry Processor Interface
- MMC - Multimedia card
- MMCC - MultiMedia Clock Controller
- MMSS - Multimedia subsystem
- MND - M/N divider
- MPM2 - SoC Master power manager. Always-on power management block.
- MPM - Master power management
- MPM - Modem power manager
- MPP - Multipurpose pin
- MPU - Memory Protection Unit
- MPU - Microprocessing unit
- MRC - Master reference code
- MSA - Modem self authentication
- MSM - Mobile Station Modem
- MTP - Media transfer protocol (USB class)
- MU-MIMO - Multi-user multiple-input, multiple-output;
N
- NIDnT - Narrow Interface for Debug and Test
- NIST - National Institute of Standards and Technology
- NIU - Network Interface Unit. The NIU is a NoC block that connects masters and
- NMEA - National marine electronics association
- NoC - Network on Chip
- NoC Master - Master Module or subsystem on the NoC capable of initiating transactions
- NoC Slave - Module or subsystem on the NoC being accessed from masters. It is the
- NPA - Node power architecture
- NS - Nonsecure
- NVIC - Nested vectored interrupt controller
O
- OBEX - Object exchange (CDC subclass)
- OCIMEM - On Chip Internal Memory
- OEM - Original equipment manufacturer
- OOO - Out of order
- OS - Operating system
- OTG - On-the-go
- OVP - Over voltage protection
P
- PA - Physical address
- PBL - Primary boot loader
- PCM - Pulse Code Modulation
- PCNOC - Peripheral and system Configuration NoC
- PDM - Pulse Density Modulation
- PDN - Power distribution network
- PD - Power domain
- PHSS - Peripheral subsystem
- PHY - Physical Layer
- PIL - Peripheral image loader
- PK - Public key
- PLL - Phase Locked Loop
- PMIC_ARB - PMIC arbiter
- PMIC - Power-Management IC. May include analog audio components such as ADC,
- POR - Power-on reset
- PPI - Private peripheral interrupt
- PRNG - Pseudo Random Number Generator
- PSCBC - Power switch clock branch cell
- PTW - Page table walk
- PubCSR - Public configuration and status register
- PVC - PMIC voltage control
- PD-MAPPER - Protection Domain Mapper
Q
- QCOM - Qualcomm
- QDSP6 - Qualcomm digital signal processor
- QDSS - Qualcomm Debug Subsystem
- QFPROM - Qualcomm fuse-programmable read-only memory
- QFROM - Qualcomm fuse programmable read-only memory
- QGIC2 - Qualcomm generic interrupt controller; compliant to ARM GIC v2.0 spec
- QGIC - Qualcomm Generic Interrupt Controller
- QMP - Qualcomm Mailbox Protocol
- QoS - Quality of service
- QSB - Qualcomm SoC Bus
- QTimer - Qualcomm timer
- QTI - Qualcomm Technologies, Inc.
- QuIC - Qualcomm Innovation Center
- QUP - Qualcomm Universal Peripheral
- Kernel docs: qcom,spi-qup.txt, qcom,i2c-qup.txt,
- See also: # GENI
R
- RAM - Random Access Memory
- RAZ - Read As Zero
- RBCPR - Rapid bridge core power reduction
- RCG - Root clock generator
- RCS - Response capable slaves
- RDI - data Raw dump interface embedded data passed to the image pipe along the pixel
- RDS - Radio data system
- RFE - Reference frame engine
- RFR - ReadyForReceive, outgoing flow control signal
- RID - ID resistor
- RIF - Register Interface
- RNG - Random Number Generator
- RPM - Resource and Power Manager
- remoteproc (cortex M3 on msm8916)
- The sw running on it allows each component in the system to vote for resources such as clocks, regulators, and bus frequencies
- Not to be confused with RPMSG
- Controlled with the
"rpm_requests"
SMD channel, either over #GLINK or #SMD - Kernel docs: qcom-rpm.txt
- RPMCC - #RPM Clock Controller
- RPMH - RPM Hardened (used in newer SoCs, like sdm845)
- RPMPD - RPM Power Domains
- RPU - Register protection unit
- RST_CTL - Reset controller
- RXLEV - This is the name of the watermark interrupt, asserted when amount of data words in the Rx FIFO exceeds the value in UART_DM_RFWR register. It is also referred to as the value in UART_DM_RFWR register.
S
- SAW2 - SPM AVS wrapper. Docs: qcom,saw2.txt
- SAW - SPM and AVS (Subystem Power Manager and Adaptive Voltage Scaling)
- SBL - Secondary boot loader
- SCMO - SDRAM Control and Memory Organizer
- SC - Single character–packing/unpacking of one character per word
- SC - Snapdragon Compute(r?)
- SDCC - Secure digital card controller
- SDCDC - Programmable delay line
- SDC - Secure digital card
- SDHCI - Secure digital host controller interface
- SDIO - Secure digital input/output
- SDP - Standard downstream port
- SDE - Snapdragon Display Engine
- SDR - Single data rate
- SD - Secure digital
- SDM - Snapdragon Mobile
- SEV - Send event
- SGI - Software generated interrupt
- SHA - Secure Hash Algorithm
- SHKE - SDRAM Housekeeping Engine
- SIF - Standard Input Format
- SIMD - Single instruction multiple data
- SIM - Subscriber identity module
- Single - character mode A UART packing/unpacking mode for both Rx and Tx channels
- SLPC - Sleep controller
- SLPI - Sensor Low Power Island
- SMD - Shared memory driver
- SMEM - Shared memory
- SMMU - System memory management unit
- SM - Sample memory
- SNOC - System NoC
- SOC - System on Chip
- SOT - Start of data transition
- SPB - Simple peripheral bus specification by Microsoft
- SPI - Shared peripheral interrupt
- SPKR - Speaker (loudspeaker)
- SPMI - System power management interface
- SPM - Subsystem Power Manager
- SPS - Smart peripheral subsystem
- SROT - Secured root of trust
- SSBI - Single-wire serial bus interface
- SSC - Snapdragon Sensor Core
- SSL - Secure Sockets Layer
- SSPP - Source surface processing pipe
- SS - Subsystem
- STB - Sensor timing strobe
- STM - System Trace Macrocell
- Sub-block - Any section of RTL code; it is typically a unit not sufficiently large and independent
- SVS - Static voltage scaling
- SWD - Serial Wire Debug
- SWFI - Suspend and wait for interrupt
- SW - Software
- SENSORS_PD - Sensors Process Protection Domain
T
- TAS - Telephony Application Server (VoLTE)
- TBU - Translation buffer unit; local page table caches
- TCM - Tightly coupled memory
- TCSR - Top level Control and Status Register
- Provides access for configuration and mux settings for a variety of peripherals.
- Kernel docs: qcom,tcsr.yaml
- TCU - Translation control unit; central page table caches
- TCXO - Crystal oscillator
- TDM - Time-division Multiplexing
- TE - Tearing Effect
- TLB - Translation lookaside buffer
- TLMM- Top-Level Mode Multiplexer
- provides pin multiplexing and pin controller
- can change signal routing on almost any physical pin
- TLS - Transport Layer Security
- TPIU - Trace Port Interface Unit
- TRM - Technical reference manual
- TSENS - Temperature sensor
- TSIF - Transport stream interface
- TXLEV - This is the name of the watermark interrupt, asserted when amount of
- TZ - TrustZone
U
- UART_DM - Universal asynchronous receiver transmitter with data mover interface
- UART - Universal asynchronous receiver/transmitter
- UAR - Universal asynchronous reset
- UHS - Ultra high speed
- UIM - User identity module
- ULPI - UTMI+ low pin interface
- ULPM - Ultra-low power mode, generally known as standby
- ULT - Audio Ultra Low-Power Audio, a version of LPASS
- USB - Universal serial bus
- UTMI - USB 2.0 transceiver macrocell interface
- USER_PD - Dynamic User Protection Domain, cases like SNPE or CV
- UE - User Equipment (VoLTE)
- UT - UE to TAS (VoLTE)
V
- VA - Virtual address
- VBIF - Virtualizing Bus Interface
- VBUS - USB bus voltage (5 V for USB 2.0)
- VCO - Voltage-controlled oscillator
- VC - Virtual channel
- VDD_CX - Digital power domain directly supplied by CXO
- VDD_MX - Memory power domain
- VDD - Supply voltage
- VENCDEC - Video encoder/decoder
- VFE - Video Front End
- VFR - Vocoder Frame Reference
- VLIW - Very long instruction word
- VLS - Voltage level shifter
- VMIDMT - Virtual machine ID mapping table
- VMID - Virtual machine identification
- VPP - Video pixel processor
- VSP - Video stream processor
- VS - Video Share (VoLTE)
- VT - Video Telephony (VoLTE)
W
- WAPI - WLAN Authentication and Privacy Infrastructure
- WB - Write buffering
- WCSSS - Wireless connectivity sub system software
- WCNSS/WCSS - Wireless Connectivity Subsystem
- WDOG - Watchdog
- WDT - Watchdog Timer
- WFE - Wait for event
- WFI - Wait for interrupt
- WI - Write Ignored
- WM - Write Master
- WLAN - Wireless local area network
X
- XO - Crystal (19.2 MHz)
- xPU - Protection Unit (x = multiple varieties; address, memory, register)