Qualcomm Glossary
See also Glossary.
A
- ACA - Accessory charger adapter
- ACC - Application Clock Controller. Docs (e.g.) qcom,kpss-acc.txt
- ACM - Abstract control model (CDC subclass)
- ACU - Access control unit
- ADC - Analog-to-digital converter
- ADMA - Advanced direct memory access
- ADP - Attach detection protocol
- ADSP - Audio Digital Signal Processor
- AHB - Advanced high performance bus; AMBA high-speed bus
- AOSS - Always-On Subsystem
- AP - Access port
- AP - Application processor
- APC - Application processor core
- APSS - Application processor subsystem
- APU - Address protected unit
- APU - Advance protection unit
- APU - Area Protection Unit
- ASM - Audio Stream Manager
- ATB - Advanced trace bus
- ATB - AMBA trace Bus
- aTCU - Application translation control unit
- AVS - Adaptive voltage scaling
- AXI - Advanced eXtensible Interface
- AUDIO_PD - Audio Process Protection Domain
B
- BAM - Bus access manager/module
- BASI - BAM-aware slave interface, between eDML and UART. Allows communication for data transfer coordination on the AHB bus.
- BCR - Backward compatibility register. Each bit in this register enables a feature/fix, that changes the behavior of the UART controller in a manner that is not backward compatible.
- BIMC - Bus Integrated Memory Controller
- BLLP - Banking or Low-Power Interval
- BLSP - BAM low speed peripherals
- BOB - BAM operational block
- BOM - Bus owner master
- BP - Baseband processors
- BR - Basic rate
- BRIC - Reusable Bus and Interconnect Components
- BTA - Bus Turnaround
- BT - Bluetooth
- BU - Bus interface unit
- BWC - Bandwidth Compression
C
- CAHB - Control AHB bus
- CAMSS - Camera subsystem
- CATS - Client-side address translation
- CBC - Clock branch cell
- CBC - Clock branch control
- CBF - Coherent bus fabric
- CCI - Camera control interface
- CCI - (Core Cluster/Cache Coherent) Interconnect (NOT msm_bus/interconnect)
- cCPU - Connectivity CPU
- CCR - Configuration control register
- CDC - Codec, Coder/Decoder
- CDC - Communications device class (USB class)
- CDP - Charging downstream port
- CGC - Clock gate control block
- CID - CSID mapped ID, which is a combination of VC and DT
- CPAS - Common platform architecture specification
- CP - Correlation processor
- CPP - Camera post processing
- CPR - Core power reduction
- CPSM - Command path state machine
- CPU - Central processing unit
- CRC-32 - 32-bit Cyclic Redundancy Check
- CRC - Cyclic redundancy check
- CRCI - Client rate control interface
- CRIF - Core register interface
- CRPC - Clock, reset, and power control
- CSR - Control and status register(s)
- CTI - cross-trigger interface
- CTM - Cross Trigger Matrix
- CTS - Clear to send–incoming flow control signal
- CURRX - Formerly known as valid_char_cnt. Amount of characters received in UART
- CXO - Core crystal oscillator
D
- DAC - digital-to-analog converter
- DAHB - Data AHB bus
- DAI - Digital Audio Interface
- DAP - Debug Access Port
- DCD - Data contact detection
- DCD - Dynamic clock divide
- DCP - Dedicated charging port
- DCS - Display Command Set
- DDR - Double data rate
- DEHR - DMA Engine for Hardware Retention
- DH - Diffie-Hellman key exchange
- DIS - Digital image stabilization
- DLL - Delay-locked loop. Delay line.
- DMA - Direct memory access
- DMB - Data memory barrier
- DM - Data mover
- DML - Data mover local
- DMRX - A target value of an Rx transfer maximal length (in characters). Value is set
- DMRX - event Occurs when CURRX value of an active RX transfer equals the DMRX
- DMRX - low event Occurs upon a write to the UART_DM_DMRX register with a value lower
- DPCM - Differential pulse-code modulation compression
- DPE - DDR Protocol Engine
- DPSM - Data path state machine
- dQH - Device queue head
- DRAM - Dynamic random-access memory
- DRNG - Deterministic Random Number Generator
- DRBG - Deterministic Random Bit Generator
- DS - Default speed
- DSI - Display Serial Interface
- DSPS - Dedicated Sensors Processor Subsystem
- DT - Data type
- dTD - Device transfer descriptor
- DTE - DDR Test Engine
E
- EBI - External bus interface
- ECC - Error Correcting Code
- ECT - Embedded cross-trigger
- ECNS - Echo cancellation and noise suppression
- eDML - Bridge between BAM and QUP I 2 C/SPI interfaces. The eDML is a master on both sides and provides service to the multiple QUPs.
- EDR - Enhanced data rate
- EE - Execution environment
- eMMC - Embedded multimedia card
- EOI - End of interrupt
- EOT - End of data transition
- EoT - End of Transmission
- eSD - Embedded secure digital
- eSDIO - Embedded secure digital input/output
- ETB - Embedded Trace Buffer
- eTD - Enhanced transfer descriptor
- ETF - Embedded Trace FIFO
- ЕТМ - Embedded trace macro
- ETR - Embedded Trace Router
F
- FDAHB - Fast data AHB bus
- FEC - Forward error correction
- FIQ - Fast interrupt request
- FM - Frequency modulation
- FPB - Fast peripheral bus
- FPS - Frames per second
- FSM - Finite State Machine
- FSUSB - Full speed USB (USB 1.0/1.1 spec and above)
G
- GCC - Global clock controller
- Kernel docs: qcom,gcc.txt
- DT Bindings: qcom,gcc.yaml
- GDHS - Globally Distributed Head Switch
- GDSC - Global distribution switch controller
- GENI - Generic Interface
- Kernel docs: qcom,geni-se.txt
- GFSK - Gaussian frequency-shift keying
- GLINK
- Fifo based mechanism for communication between subsystems on Qualcomm platforms
- Kernel docs: qcom,glink.txt
- GNSS - Global navigation subsystem
- GPIO - general-purpose input/output
- GPO - general-purpose output
- GPU - Graphic Processing Unit
- GSBI - General serial bus interface
- gTCU - Graphics translation control unit
H
- HBP - Horizontal back porch
- HFP - Horizontal front porch
- HLOS - High-level operating system
- HPH - Headphone
- HPI - High priority interrupt
- HSA - Horizontal Sync Active
- HS - High speed
- HS - High-speed USB (USB 2.0 spec and above)
- HUM - Hit under miss
- HW - Hardware
I
- I2S - Inter-IC Sound, specification for serial, stereo audio transfer
- IC - Integrated circuit
- IDLT - Idle timer
- IKE - Internet Key Exchange
- IM - Integration module
- IPA - Intermediate physical address
- IPC - Interprocess communication
- IPC - Interprocessor communication
- IP - Intellectual Property (also known as a core or a block)
- IrDA - Infrared data association
- IRQ - Interrupt Request
- ISDB - In silicon debugger
- ISPIF - Image signal processors interface
- ISR - Interrupt service routine
- ITM - Interrupt transfer mode
J
- JDR - JTAG data registers
- JEITA - Japan Electronics and Information Technology Industries Association
- JPEG - Joint Photographic Experts Group
- JTAG - Joint Test Action Group (ANSI/ICEEE Std. 1149.1-1760)
K
- KVP - Key value pairs
L
- L2VIC - Second-level vector interrupt controller
- LA - Linux for Android
- LAB/IBB - LCD Amoled Boost / Inverting Buck Boost (type of regulator)
- LCD - Liquid Crystal Display
- LDO - Low dropout (voltage regulator)
- LE - Low energy
- LFSR - Liner Feedback Shift Register
- LPAE - Large physical address extension
- LPA_IF - Low-Power Audio Interface
- LPA - Low-Power Audio
- LPASS - Low-Power Audio Sub-System
- LP - Low-power
- LPM - Link power management
- LPM - Low-Power Memory
- LS - USB Low speed USB (USB 1.0/1.1 spec and above)
- LTE - Long Term Evolution
- LUT - Look up table
M
- MAC - Media access control layer
- MBA - Modem boot authentication
- MCLK - Secure digital interface clock
- MC - Micro controller
- MCU - Minimum coded units
- MDP - Mobile Display Processor in MDSS
- MDSS - Mobile Display Subsystem
- MGPI - Multi generic-event PMIC_ARB Interface
- MI2S - Multichannel I2S
- MIC - Microphone
- MID - Master ID
- MIPI - Mobile Industry Processor Interface
- MMC - Multimedia card
- MMCC - MultiMedia Clock Controller
- MMSS - Multimedia subsystem
- MND - M/N divider
- MPM2 - SoC Master power manager. Always-on power management block.
- MPM - Master power management
- MPM - Modem power manager
- MPP - Multipurpose pin
- MPU - Memory Protection Unit
- MPU - Microprocessing unit
- MRC - Master reference code
- MSA - Modem self authentication
- MSM - Mobile Station Modem
- MTP - Media transfer protocol (USB class)
- MU-MIMO - Multi-user multiple-input, multiple-output;
N
- NIDnT - Narrow Interface for Debug and Test
- NIST - National Institute of Standards and Technology
- NIU - Network Interface Unit. The NIU is a NoC block that connects masters and
- NMEA - National marine electronics association
- NoC - Network on Chip
- NoC Master - Master Module or subsystem on the NoC capable of initiating transactions
- NoC Slave - Module or subsystem on the NoC being accessed from masters. It is the
- NPA - Node power architecture
- NS - Nonsecure
- NVIC - Nested vectored interrupt controller
O
- OBEX - Object exchange (CDC subclass)
- OCIMEM - On Chip Internal Memory
- OEM - Original equipment manufacturer
- OOO - Out of order
- OS - Operating system
- OTG - On-the-go
- OVP - Over voltage protection
P
- PA - Physical address
- PBL - Primary boot loader
- PCM - Pulse Code Modulation
- PCNOC - Peripheral and system Configuration NoC
- PDM - Pulse Density Modulation
- PDN - Power distribution network
- PD - Power domain
- PHSS - Peripheral subsystem
- PHY - Physical Layer
- PIL - Peripheral image loader
- PK - Public key
- PLL - Phase Locked Loop
- PMIC_ARB - PMIC arbiter
- PMIC - Power-Management IC. May include analog audio components such as ADC,
- POR - Power-on reset
- PPI - Private peripheral interrupt
- PRNG - Pseudo Random Number Generator
- PSCBC - Power switch clock branch cell
- PTW - Page table walk
- PubCSR - Public configuration and status register
- PVC - PMIC voltage control
- PD-MAPPER - Protection Domain Mapper
Q
- QCOM - Qualcomm
- QDSP6 - Qualcomm digital signal processor
- QDSS - Qualcomm Debug Subsystem
- QFPROM - Qualcomm fuse-programmable read-only memory
- QFROM - Qualcomm fuse programmable read-only memory
- QGIC2 - Qualcomm generic interrupt controller; compliant to ARM GIC v2.0 spec
- QGIC - Qualcomm Generic Interrupt Controller
- QMP - Qualcomm Mailbox Protocol
- QoS - Quality of service
- QSB - Qualcomm SoC Bus
- QTimer - Qualcomm timer
- QTI - Qualcomm Technologies, Inc.
- QuIC - Qualcomm Innovation Center
- QUP - Qualcomm Universal Peripheral
- Kernel docs: qcom,spi-qup.txt, qcom,i2c-qup.txt,
- See also: # GENI
R
- RAM - Random Access Memory
- RAZ - Read As Zero
- RBCPR - Rapid bridge core power reduction
- RCG - Root clock generator
- RCS - Response capable slaves
- RDI - data Raw dump interface embedded data passed to the image pipe along the pixel
- RDS - Radio data system
- RFE - Reference frame engine
- RFR - ReadyForReceive, outgoing flow control signal
- RID - ID resistor
- RIF - Register Interface
- RNG - Random Number Generator
- RPM - Resource and Power Manager
- remoteproc (cortex M3 on msm8916)
- The sw running on it allows each component in the system to vote for resources such as clocks, regulators, and bus frequencies
- Not to be confused with RPMSG
- Controlled with the
"rpm_requests"
SMD channel, either over #GLINK or #SMD - Kernel docs: qcom-rpm.txt
- RPMCC - #RPM Clock Controller
- RPMH - RPM Hardened (used in newer SoCs, like sdm845)
- RPMPD - RPM Power Domains
- RPU - Register protection unit
- RST_CTL - Reset controller
- RXLEV - This is the name of the watermark interrupt, asserted when amount of data words in the Rx FIFO exceeds the value in UART_DM_RFWR register. It is also referred to as the value in UART_DM_RFWR register.
S
- SAW2 - SPM AVS wrapper. Docs: qcom,saw2.txt
- SAW - SPM and AVS (Subystem Power Manager and Adaptive Voltage Scaling)
- SBL - Secondary boot loader
- SCMO - SDRAM Control and Memory Organizer
- SC - Single character–packing/unpacking of one character per word
- SC - Snapdragon Compute(r?)
- SDCC - Secure digital card controller
- SDCDC - Programmable delay line
- SDC - Secure digital card
- SDHCI - Secure digital host controller interface
- SDIO - Secure digital input/output
- SDP - Standard downstream port
- SDR - Single data rate
- SD - Secure digital
- SDM - Snapdragon Mobile
- SEV - Send event
- SGI - Software generated interrupt
- SHA - Secure Hash Algorithm
- SHKE - SDRAM Housekeeping Engine
- SIF - Standard Input Format
- SIMD - Single instruction multiple data
- SIM - Subscriber identity module
- Single - character mode A UART packing/unpacking mode for both Rx and Tx channels
- SLPC - Sleep controller
- SLPI - Sensor Low Power Island
- SMD - Shared memory driver
- SMEM - Shared memory
- SMMU - System memory management unit
- SM - Sample memory
- SNOC - System NoC
- SOC - System on Chip
- SOT - Start of data transition
- SPB - Simple peripheral bus specification by Microsoft
- SPI - Shared peripheral interrupt
- SPKR - Speaker (loudspeaker)
- SPMI - System power management interface
- SPM - Subsystem Power Manager
- SPS - Smart peripheral subsystem
- SROT - Secured root of trust
- SSBI - Single-wire serial bus interface
- SSC - Snapdragon Sensor Core
- SSL - Secure Sockets Layer
- SSPP - Source surface processing pipe
- SS - Subsystem
- STB - Sensor timing strobe
- STM - System Trace Macrocell
- Sub-block - Any section of RTL code; it is typically a unit not sufficiently large and independent
- SVS - Static voltage scaling
- SWD - Serial Wire Debug
- SWFI - Suspend and wait for interrupt
- SW - Software
- SENSORS_PD - Sensors Process Protection Domain
T
- TAS - Telephony Application Server (VoLTE)
- TBU - Translation buffer unit; local page table caches
- TCM - Tightly coupled memory
- TCSR - Top level Control and Status Register
- Provides access for configuration and mux settings for a variety of peripherals.
- Kernel docs: qcom,tcsr.txt
- TCU - Translation control unit; central page table caches
- TCXO - Crystal oscillator
- TDM - Time-division Multiplexing
- TE - Tearing Effect
- TLB - Translation lookaside buffer
- TLMM- Top-Level Mode Multiplexer
- provides pin multiplexing and pinctrl
- can change signal routing on almost any physical pin
- TLS - Transport Layer Security
- TPIU - Trace Port Interface Unit
- TRM - Technical reference manual
- TSENS - Temperature sensor
- TSIF - Transport stream interface
- TXLEV - This is the name of the watermark interrupt, asserted when amount of
- TZ - TrustZone
U
- UART_DM - Universal asynchronous receiver transmitter with data mover interface
- UART - Universal asynchronous receiver/transmitter
- UAR - Universal asynchronous reset
- UHS - Ultra high speed
- UIM - User identity module
- ULPI - UTMI+ low pin interface
- ULPM - Ultra-low power mode, generally known as standby
- ULT - Audio Ultra Low-Power Audio, a version of LPASS
- USB - Universal serial bus
- UTMI - USB 2.0 transceiver macrocell interface
- USER_PD - Dynamic User Protection Domain, cases like SNPE or CV
- UE - User Equipment (VoLTE)
- UT - UE to TAS (VoLTE)
V
- VA - Virtual address
- VBIF - Virtualizing Bus Interface
- VBUS - USB bus voltage (5 V for USB 2.0)
- VCO - Voltage-controlled oscillator
- VC - Virtual channel
- VDD_CX - Digital power domain directly supplied by CXO
- VDD_MX - Memory power domain
- VDD - Supply voltage
- VENCDEC - Video encoder/decoder
- VFE - Video Front End
- VFR - Vocoder Frame Reference
- VLIW - Very long instruction word
- VLS - Voltage level shifter
- VMIDMT - Virtual machine ID mapping table
- VMID - Virtual machine identification
- VPP - Video pixel processor
- VSP - Video stream processor
- VS - Video Share (VoLTE)
- VT - Video Telephony (VoLTE)
W
- WAPI - WLAN Authentication and Privacy Infrastructure
- WB - Write buffering
- WCSSS - Wireless connectivity sub system software
- WCNSS/WCSS - Wireless Connectivity Subsystem
- WDOG - Watchdog
- WDT - Watchdog Timer
- WFE - Wait for event
- WFI - Wait for interrupt
- WI - Write Ignored
- WM - Write Master
- WLAN - Wireless local area network
X
- XO - Crystal (19.2 MHz)
- xPU - Protection Unit (x = multiple varieties; address, memory, register)