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{{Infobox soc
| name = Tegra 2
| manufacturer = Nvidia
| arch = armv7
| image = File:NVIDIA T20 chip.jpg
| imagecaption = NVIDIA T20 chip
| year = 2010
| cpu = 2x 1.0/1.2 GHz ARM Cortex-A9
| community_page = https://github.com/grate-driver
| gpu = Nvidia ULP Geforce
| process = 40
| mainline = yes
| status_cpu = Y
| status_uart = Y
| status_storage = Y
| status_usb = Y
| status_display = Y
| status_gpu = P
| status_pinctrl = Y
| status_i2c = Y
| status_audio = Y
| status_video = Y
| status_thermal = Y
| status_wifi = -
| status_bluetooth = -
| status_modem = -
| status_gps = -
| status_camera = P
| status_suspend = Y
}}
== Development ==
=== Bootloader ===
Currently except classic proprietary Aboot (using fastboot service), there is open-source [http://www.denx.de/wiki/U-Boot u-boot] development in progress for some Tegra devices. You can check [https://github.com/clamor-s/u-boot/commits/tf101 repository]


== Graphics ==
#REDIRECT [[Nvidia Tegra 2/3/4]]
=== Components [https://github.com/grate-driver/ (source)] ===
* Mesa-3D (minimal implementation, not complete enough (GL 1.4) to run XWayland (requires GL 2.1 or GLES2)
* xf86-video-tegra (2D acceleration for X11, EXA)
* libvdpau-tegra
 
=== Usability ===
Wayland:
* Phosh works, but UI is accelerated trough llvmpipe (software rendering), thus is slow.
* Plasma mobile not tested (please update)
 
X11:
* Xfce4 and Mate desktop will run on 2D acceleration.
* Hildon requires an OpenGL backend.
** As of cogl 1.22.2 the clutter/cogl backend requires stencil buffers (<code>EGL_STENCIL_SIZE</code>). This not yet implemented in the grate-driver.
 
=== Video Decoding ===
 
Video Decoder Engine (VDE) was added to mainline kernel v4.16. The grate-driver includes hardware h264 decoding with libvdpau-tegra.
 
The vdpau driver does '''not''' support h264 videos encoded with:
* weighted prediction
* CABAC
 
Sample video that can be decoded with hardware acceleration:
https://peach.blender.org/trailer-page/
 
<source lang="shell">
$ mpv --hwdec=vdpau trailer_720p.mov
Using hardware decoding (vdpau).
VO: [vdpau] 1280x720 vdpau[yuv420p]
</source>
 
== Participate development ==
=== Develop ===
==== Mesa3D Gallium driver ====
https://github.com/grate-driver/mesa
 
* Host1x ABI rework (required before mesa implemenetation): [https://docs.google.com/document/d/1hj7-Bup1NtjJVHzGvs92kTkah0EEh_9wDHBsQWUkuwo/edit (G. docs)]
* migrate from TGSI to NIR
* establishing demos that work, where can be seen regression
 
 
==== New Device Trees ====
To generate the correct RAM timings for new Tegra 3 devices from known kernel sources, you can start from the known (downstream) RAM model code, and generate valid timings using this tool by Ion Agorria: https://gitlab.com/IonAgorria/tegra-timings-generator.
 
The #postmarketOS-on-transformers:matrix.org chat room will also be an excellent starting point for the porting of any new Tegra 2/3/4 device, also outside strictly the ASUS Transformer series
 
== Devices with a Tegra 2 Chipset ==
{{#cargo_query:
tables=Devices
|fields=CONCAT( '[[', _pageName, '|',Manufacturer,' ',Name,']]' )=Device,StatusMainline=Mainline
|order by=Devices.Manufacturer, Devices.Name
|format=table
|limit=9999
|where=Devices.chipset like '%Nvidia Tegra 2%'
|more results text=
}}
 
== See also ==
* Tegra 2's Cortex A9 implementation does not include ARM's SIMD extension, NEON. [https://en.wikipedia.org/wiki/Tegra More info here]
* Tegra 2 is very similiar to [[Nvidia_Tegra_3_(tegra30)]]

Latest revision as of 09:41, 25 August 2024

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